1. Field of the Invention
The present invention relates in general to a method for automatically generating a partitioned integrated circuit layout, and in particular to a method which automatically establishes separate timing criteria for each circuit partition.
2. Description of Related Art
The IC Design Process
An integrated circuit (IC) designer typically produces a high level xe2x80x9cregister transfer languagexe2x80x9d (RTL) netlist describing an IC only in terms of the logic it carries out. For example when a signal appearing at a node C of the circuit is to be the logical AND of signals appearing at circuit nodes A and B, an RTL netlist may describe the portion of the circuit to carry out that operation gate by using only the simple logic equation C=A*B. To test the logic of the circuit described by the netlist, the designer supplies the netlist and a xe2x80x9ctestbenchxe2x80x9d file as inputs to a circuit simulator. The circuit simulator then simulates the behavior of the circuit described by the netlist in response to a set of input signals described by the testbench file and produces output data describing the behavior of signals at various nodes of the circuit. However since the netlist models the AND gate as simple boolean operator, the simulator cannot take into account the actual switching speed of the AND gate when modeling circuit behavior.
Having used the simulator to verify the logic of the circuit, the designer uses xe2x80x9csynthesisxe2x80x9d CAD tools to create a xe2x80x9cgate-levelxe2x80x9d netlist modeling the time-dependent behavior of the logic gates and other components (cells) needed to implement the logic defined by the RTL netlist. Boolean logic models of the RTL netlist are replaced in the gate level netlist with mathematical models provided by the cell library that reflect the time-dependent behavior of the cells. For example, instead of an RTL model of an AND gate as a simple boolean function C=A*B, the gate level netlist will model the AND gate with a mathematical expression having time as a variable and which describes the gate""s input and output signals as analog voltages that ramp up or down over time in response to changes in input signal voltages. This more detailed netlist model of the circuit enables the circuit simulator to more accurately verify not only the circuit""s logic but also the time-dependent behavior of the circuit. The designer can then use the simulator to test not only the circuit""s logic, but also whether the circuit meets various timing constraints that the designer has imposed on the design. Each timing constraint typically places a maximum limit on the amount of time a signal needs to pass through a series of gates forming a particular signal path within the IC.
After using the simulator to verify the time-dependent behavior of the circuit described by the netlist, the circuit designer typically uses an automated placement and routing tool to convert the gate level netlist into an IC layout. The layout indicates how and where each cell is to be formed within the IC substrate and describes the signal routing structures within the IC that are to interconnect the cells. A typical placement and routing tool uses an algorithm which iteratively moves cells about on the substrate looking for a placement solution wherein all cells fit within the substrate area allocated for the placement, wherein the cells are properly interconnected, and wherein all timing and other constraints that the designer has imposed on the layout. Other constraints may include, for example, constraints on IC die size, power consumption, clock skew, and signal integrity.
While the gate level netlist upon which the layout is based accurately describes the time-dependent behavior of the cells, it does not accurately account for the time-dependent behavior of routing structures that interconnect the cells since the lengths and impedance characteristics of those structures are not known until the placement and routing tool lays out those structures. However the placement and routing tool attempts to position cells and design interconnect structure so as to satisfy various timing constraints for the signal paths they form.
Once the placement and routing tool has created an IC layout, the designer may use a netlist compiler to convert the layout back into another netlist that is similar to the gate level netlist, but which also accurately models the time-dependent behavior of the routing structures that interconnect the cells. The designer may then again use circuit simulation and timing verification tools to check the whether the circuit as laid out will satisfy its timing constraints as expected before sending the completed IC layout to an IC manufacturer.
As ICs become larger and more complex, it takes more time and processing power to convert a netlist into a layout. It can be quicker to separately lay out several small partitions of an IC than to layout the entire IC all at once, but a designer can find it difficult to determine how to best partition a circuit design and to accurately estimate the size, shape and position of the substrate area each partition will need. A designer can find it even harder to determine how to partition circuit timing constraints. When portions of a signal path for which there is a timing constraint are implemented within two or more partitions, the designer has to determine how much of the signal path""s timing constraint should be allocated to each partition. The time required for a signal to travel through a set of logic gates forming a signal path depends not only on the switching delay of each gate, but also on the delays of the routing structures interconnecting those gates. Thus to allocate a timing constraint to portions of a signal path residing within two or more partitions, the designer needs to determine which gates are to be included within each partition and the delay of each gate. The designer would like to know the delays associated with the routing structures within and between each partition that interconnect those gates. However since the routing structures are designed during the layout process, it is difficult for the designer to estimate what those delays might be before the layout process begins.
What is needed is a method for automatically partitioning a circuit design and for allocating timing constraints between partitions in a manner that improves the chances that a full-chip layout incorporating all of the partition layouts will satisfy all of the circuit""s timing constraints.
The invention relates to a method for generating an integrated circuit (IC) layout for an IC design modeling an IC as a logical hierarchy of modules and including a set of timing constraints specifying maximum signal path delays for various signal paths within the IC.
A computer system implementing an IC layout method in accordance with the invention, initially generates a full-chip trial layout indicating the position of each cell in the substrate and describing routing structures interconnecting the cells. The trial layout need only satisfy various constraints that are usually relatively easy to satisfy, such as die size, power consumption, clock skew, and signal integrity. However since the trial layout need not necessarily satisfy all of the circuit""s timing constraints, which are often relatively hard to satisfy, the system can generate the full-chip trial layout very quickly.
After generating the trial layout, the system automatically divides the IC design into a set of partitions. Since cells of a module tend to be highly interconnected with one another, and since it is preferable to minimize the number of signal paths linking partitions, the system divides the design along modular lines at the highest levels of the modular hierarchy for which the method can produce partitions that are roughly equal in size. Also since modules appearing near one another in the trial layout tend to be highly interconnected with one another, the system also tries to group modules appearing near one another in the trial placement together in the same partition.
After developing a partition plan, the system develops a floorplan allocating an appropriate amount of substrate area to each module. Since the trial layout tends to cluster cells of the same module of the circuit design near one another, the system is able to estimate the size shape of substrate areas needed to implement each module based on the size and shape of the substrate area spanned by cells forming each module within the trial layout.
The system also produces a timing budget for each signal path for which the circuit design includes a timing constraint. When sections of a signal path appear in more than one partition, the timing budget allocates a separate portion of the signal path""s timing constraint to each path section. The amount of the maximum allowable signal path delay allocated to each section is proportional to the estimated path delay of the section, based on the delays of gates and of routing structures forming the path section in the trial layout.
The system then generates a separate layout for each partition, and in doing so, attempts to position and interconnect cells forming each signal path so as to satisfy the partition""s timing budget. The individual partition layouts are combined to form a full-chip layout
If the full-chip layout satisfies all of the circuit""s timing and other constraints, then it is provided as the system""s output layout for the IC. However if the full-ship layout does not""satisfy all constraints, then the process of partitioning the design, creating a timing budget, and separately laying out each partition is repeated. However prior to this second iteration of the process, the system recompiles the last generated full-chip layout back into a netlist description of the circuit, which now includes more detailed descriptions of the signal interconnect paths. It then produces a new trial layout based on the improved netlist uses the new trial layout, as a basis for determining how to partition the design and for developing a timing budget. The new trial layout is likely to be a more accurate predictor of module area requirements and path delays than the initial trial layout. The system iteratively repeats partitioning, time budgeting and layout process until it converges an modular layout satisfying the circuit""s constraints.
It is accordingly an object of the invention to provide a method for use by a computerized placement and routing system, for automatically dividing a circuit design into partitions and for allocating timing constraints between partitions so that the placement and routing system can separately place and route each partition.